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EN0-001 Online Practice Questions and Answers

Questions 4

When debugging an embedded Linux system, which one of the following techniques can be used to halt a single user thread, while allowing other threads to continue to run during the debug process?

A. Halting a single user thread in an embedded Linux system is not possible

B. Use the Linux kernel printk() function to output messages to the console

C. Connect a Linux-aware JTAG debugger to the target, which allows single-stepping of the code

D. Connect a debugger running on an external host device to an instance of gdbserver running on the target, using Ethernet

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Questions 5

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

A. Instruction cache clean only

B. Instruction cache invalidate only

C. Data cache clean and instruction cache invalidate

D. Data cache invalidate and instruction cache invalidate

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Questions 6

Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?

A. A dedicated real-time clock to provide the total cycle count

B. Use of the divide-by 64 counting option to avoid an overflow of the cycle counter

C. Use of the overflow interrupts, to extend the range of the built-in 32-bit counter

D. Modification of the application software being profiled, to insert timestamps at regular intervals

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Questions 7

Which instruction would be used to return from a Reset exception?

A. MOVS PC, R14

B. MOVSPC, R13

C. Architecturally not defined

D. SUBS PC, R14, #4

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Questions 8

The following function is declared: float func(float fl, float f2);

The file file1 .c contains a call to func, and is compiled with hard floating point linkage. The file file2.c contains the definition of func, and is compiled with AACPS soft floating point linkage.

Assume that the two files are successfully linked using the ARM linker and an executable is generated. The generated executable:

A. Exhibits correct behavior, but suffers a performance penalty because the linker has to generate extra code.

B. Exhibits correct behavior, and suffers no performance penalty.

C. Will not execute.

D. Exhibits incorrect behavior.

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Questions 9

The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.

In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?

A. WFENE at , SEV at

B. WFEEQ at SEV at

C. WFE at SEV at WFENE at

D. SEV at

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Questions 10

When linking with the standard C library, which library functions MUST be redefined in order to port your code to a new piece of production hardware?

A. Functions that are not compliant with the ISO C library standard

B. Functions that are not compliant with the 1985 IEEE 754 standard for binary floating-point arithmetic

C. Target-dependent functions which use semihosting

D. Functions called implicitly by the compiler

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Questions 11

Cross compiling enables a programmer to:

A. Produce a binary object that will run on processors based on any architecture.

B. Mix different source languages within the same source file and compile with a single tool.

C. Run code written for one processor on a processor based on a different architecture.

D. Compile target code using a computer based on a different architecture.

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Questions 12

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

A. 5 cycles

B. 7 cycles

C. 8 cycles

D. 15 cycles

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Questions 13

Which of the following is an external exception?

A. Supervisor Call

B. FIQ

C. Undefined Instruction

D. Parity

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Exam Code: EN0-001
Exam Name: ARM Accredited engineer
Last Update: Apr 23, 2024
Questions: 210
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