EN0-001 Online Practice Questions and Answers

The following function is declared: float func(float fl, float f2);

The file file1 .c contains a call to func, and is compiled with hard floating point linkage. The file file2.c contains the definition of func, and is compiled with AACPS soft floating point linkage.

Assume that the two files are successfully linked using the ARM linker and an executable is generated. The generated executable:

A. Exhibits correct behavior, but suffers a performance penalty because the linker has to generate extra code.

B. Exhibits correct behavior, and suffers no performance penalty.

C. Will not execute.

D. Exhibits incorrect behavior.

During an investigation into a software performance problem an engineer doubles the clock frequency of a cached ARM processor running the software. Unfortunately the performance of the application does not increase by very much, despite running on the processor for 100% of the time. What is likely to be the main bottleneck in the system?

A. The processor is context switching between multiple processes

B. Performance is limited by the speed of external memory

C. The processor is taking too long to execute branch instructions

D. The system is raising interrupts too fast for the processor to handle them

If the processor is in User mode and then an IRQ interrupt occurs:

A. CPSR mode bits are set to User mode and SPSR _User mode bits are set to IRQ.

B. CPSR mode bits are set to IRQ and SPSR_Irq mode bits are set to User.

C. CPSR mode bits are set to IRQ and SPSR_Irq mode bits are set to IRQ.

D. CPSR mode bits are set to User and SPSR User mode bits are set to IRQ.

What type of instruction is used for cache maintenance operations?

A. Dedicated ARM instructions

B. Dedicated Thumb instructions

C. CP14 instructions

D. CP15 instructions

An undefined instruction will cause an Undefined Instruction exception to be taken when:

A. It is fetched.

B. It is decoded.

C. It is executed.

D. It writes back its results.

As part of the ABI specification, the AAPCS defines which of the following?

A. How many levels of nested function calls are permitted on ARM systems

B. How to measure the maximum amount of stack required by an application

C. On which mode's stack you need to save the return address in a non-leaf function

D. Which registers need to be preserved by a function

Which of the following statements is TRUE with respect to the power consumption related to memory accesses?

A. Accessing a large memory device consumes less power than accessing a small one

B. A series of non-sequential accesses is more efficient than a series of sequential accesses

C. Increasing the size of the cache will always reduce power consumption for a given application

D. Storing frequently used data in Tightly Coupled Memory will reduce power consumption

Which of these items is typically shared between threads running in the same Operating System (OS) process?

A. Stack

B. Memory map

C. Register values

D. Program Counter

Which of the following features was added in version 2 of the ARM Architecture Advanced SIMD extensions?

A. Additional quadword registers

B. Support for double precision floating-point arithmetic

C. Fused Multiply-Accumulate (Fused MAC) instructions

D. Support for polynomials

Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

A. Memory read instructions, and memory write instructions

B. Architecturally executed instructions, and instruction fetches causing a cache line refill

C. Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

D. Memory read or write operations causing a cache access, and architecturally executed instructions